New Mercury Cadmium Telluride Nanowire based photo detector has been implemented horizontally Simulations have been carried out using optical model.Master of Science thesis on “Exploration of 3D Nanowire Image sensor and circuitry to enable logic and sensing in single chip”.TCAD based simulations of 3D Image sensor, integration of sensor and circuitry in a single chip.Programming Languages: C, Assembly Language, Embedded TCAD Tools Synopsys: Sentaurus Process, Sentaurus Device, Sentaurus Structure Hardware Platforms: Basys, Basys 2, Spartan 3E, Spartan 2, Vertex5, Arduino.ĮDA Tools Cadence: SOC Encounter, RTL Compiler, Virtuoso, Layout XL, Spectre Knowledge in Designing Nano scale sensors and exploring new devices. Hands on experience with clean room and fabrication process.Expert in handling bunch of Test cases, reporting the bugs, running regression testing and coverage.
#Pong game code in vhdl full
Strong knowledge ASIC/ FPGA pre silicon verification with Full constraint random testing, coverage based verification.Strong expertise in IP Verification, SV Assertions, Functional Coverage and Low Power Verification.Well versed with System Verilog and progressive experience with UVM test methodologies.Over 7 years of experience in ASIC Verification, RTL Design including design specification, RTL coding, simulation, synthesis, logic equivalence check and power analysis.Surveillance system capable of finding a person as he or she moves across a network of CCTV cameras Using Deep Learning.
Our project "Person Re-Identification using Multiple Cameras" is an intelligent video In the course of Mobile Communication, Our group surveyed by reading research papers and gave presentation on wireless and mobile communication security covering from 1G to 5G security vulnerabilities.Ħ-PERSON RE-IDENTIFICATION USING MULTIPLE CAMERAS.
through web based AdaFruit server and google voice assistant commands. The project is done in Electronic Circuit Design Course for IOT based home automation system Using NODEMCU for sensing of more than 4 sensors and control of lights, fans, etc. In 1st phase of Project, most famous cryptographic algorithms including AES, SHA-3, ECDH and RSA are to be programmed in c and python and in 2nd phase their pipelined architectures are to be designed in Verilog. The goal of this project is to design accelerated pipelined Hardware Architecture Designs for Cryptography. The project is done in Embedded system design course for implementation of POST- QUANTUM Cryptography schemes focusing on lattice based algorithms on ARM cortex m4 in C and they are bench-marked against each other in terms of memory size, speed and stack size. POST-QUANTUM CRYPTOGRAPHY ON ARM-CORTEX-M4 The Project is done in Embedded system design course for design of 5- stage pipelined RISC-V processor in Verilog supporting all formats of 32IM of RISC-V ISA. Verilog,VHDL,C++, C,x86 assembly, RISC-V assembly,MIPS assembly,ARM assembly, python automation, bash scripting, Keras, Tensorflow, Ghidra NSA reverse engineering suite, Linux CLI, Burp Suite, Wireshark,OSINT,Shodan ,Computer Architecture,Cryptography,Electronic Circuit Design, Embedded Systems, Computer Security,Malware Analysis, Accelerated Hardware Architecture Designs(ASIC,FPGA) Intel Quartus prime,Xilinx Vivado,ModelSim more about the product details
#Pong game code in vhdl series
Highly optimized and Pipelined Architectures of FPGAġ- RISC-V 5- stage pipelined RISC-V processor in VerilogĢ-CRYPTOGRAPHYic Algorithms AES,RSA,ECDH,SHA-3 were implemented in Verilog and VHDL.ģ-Verilog implementation of SneakySnake pre-alignment filtering algorithm for Genome Sequencingĥ-Oven Design implementation in altera DE-10-LiteĪltera DE-x series and Xilinx vertex-7 FPGA I would provide from simple to Accelerated Pipelined Hardware Architecture Designs in Verilog from simple Circuit Designs to Complete Processor with highly optimized verilog Codeĭesign RISC-V and MIPS Custom processor Datapath and Control. I would provide verilog code for following areasĭigital logic design logic using verilog HDLĬomputer Architecture tasks using Verilog HDLĬomputer organization tasks using Verilog HDL